1. Field of the Invention
The present invention relates to apparatus for addressing rows of memory cells in general and to a memory device comprising an apparatus for selectively addressing redundant rows of memory cells in particular.
2. Description of Prior Art
A digital memory of the type to which the present invention relates comprises a plurality of rows and columns of memory cells which are fabricated on a solid-state chip. Typically, the contents of the cells in each row comprise a data word.
In a typical embodiment of such a memory, the rows of cells are functionally divided between a first and a second set of cells. For example, in a memory comprising 32 rows of cells for storing 32 data words, 16 rows are located in the first set of cells and 16 rows are located in the second set of cells. To address a particular row in either set, a five bit address A.sub.0 -A.sub.4 is used wherein the most significant bit A.sub.4 defines the set in which the row is located. For example, if the rows in each set are stacked in a numerically ascending order with the lowest order row at the top of each stack, the fifth row from the top of the stack in the first set would have the A.sub.0 -A.sub.4 address 10100, whereas the same row in the second stack would have the A.sub.0 -A.sub.4 address 10101.
As memory densities increased, it became economically impractical to discard a memory simply because one or more cells in one or more rows was defective.
One of the techniques used to avoid discarding a memory because of the existence of one or more defective rows of cells in the memory was to include in the fabrication of the memory on each chip a plurality of regular rows of memory cells and one or more redundant rows of cells which could be used in place of a defective regular row.
In the development of a memory using the latter technique, commonly called direct fusing, a fuse was provided in each of the regular rows of memory cells. After fabrication and testing of the memory, if a regular row in the memory was found to contain a defective cell, the fuse associated with that row was blown, disabling the row, and one of the redundant rows was enabled to respond to the address of the defective regular row. The apparatus used for enabling the redundant row to respond to the address of a defective regular row was called a redundant row decoder.
As the need for even higher memory densities developed, the space required to use fuses for disabling defective regular rows in a memory became impractical and another technique for disabling defective regular rows and addressing redundant rows was developed. This technique is commonly called indirect fusing.
In the implementation of the conventional indirect fusing technique there was provided on a solid-state chip a plurality of regular rows of memory cells and one or more redundant rows of memory cells, a regular row decoder and a redundant row decoder. The regular rows and the redundant rows used for replacing a defective regular row were coupled to the same bit lines.
After fabrication and, if in testing, a regular row in a memory using the conventional indirect fusing technique was found defective, the redundant row decoder was enabled to respond to the address of the defective regular row, as by the blowing of selected fuses provided therein for that purpose.
In the operation of a memory embodying the indirect fusing technique, when the address of a defective regular row was applied to the memory, the redundant row decoder, which was enabled to respond to the address of the defective regular row, would respond to the address and at the same time provide a disabling signal for disabling the regular row decoder used for addressing all of the regular rows.
While eliminating the need for fuses in each of the regular rows and thereby conserving space on the chip, it was found that in practice, the time required for disabling the regular row decoder in a memory using the conventional indirect fusing technique was relatively long such that, for at least a brief period of time, the defective regular row and a redundant row which had been enabled to respond to the address of the defective regular row would both produce signals on the bit lines to which they were coupled in parallel when the defective regular row was addressed. When this occurred and there was inconsistent data in corresponding cells in the defective regular row and the redundant row, e.g. a logical 1 in one of the rows and a logical 0 in the other, erroneous or unreadable data signals could appear on the bit lines to which the redundant and regular rows were coupled.